Juan and David did some more renaming on Wednesday so today I will pick up where they left off.
Starting with the hs_components block I and going to add output pins to all of the components. 20 for each ICDP and 4 for the TSDP so 64 pins in total.... renamed all the output pins from c1i1 to c1o2 since they are outputs and not input. Applied this to all output pins on this block. Realized we may not need these inputs since the icdp and tsdp all take the same cscnt_sum and carry signal. Created different pulse values for each input
Added differing pulse lines to each of the se_pulse_preps c1i1_pulse_in etc for each of the data paths and timing path. Renamed the signals coming into the se_pulse's "PLL_clk" to match the high speed clk signal coming out from the high speed time counter.
Spent a lot of time checking line paths and updating a few more lines in the other HS block component levels. Will have to pick up some more next week. Have to spend some time on my E-fields lab pre-lab before that class starts.
From this description, I can't tell if you did it right, because the NEW icdp/tsdp (with the pulse-cap modules extracted) will of course not have the same inputs as the old ones - in particular, it is no longer true that they all just take the same counter sum and carry - since those are the signals that went to the front-end pulse_cap module which you extracted. Whoever comes in first next week, we need to sit down together and review the current design to make sure it is correct. Regards, -Mike
ReplyDeleteOK, I thought they were supposed to get different sum and carry values so currently the pins for that design idea are still there since it took a long time to design that way. I was going to talk to you on Tuesday and see if it should be different than that before I removed them for good so i'm glad I didn't delete the pins. We can discuss it some more to clear any confusion I may have in the redesigning of the project.
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