Working on Logic Lock

After some testing and debugging Dr. Frank solved the issue that was occurring with Darryl, David and I's changes to the Timing Sync Datapath and test VHDL code.  Since that is working we are moving on to the next few steps.  The nearest projected self imposed deadline is:

"On or before Wednesday Feb 8th: Demonstrate the 56-bit high-speed counter running at 500MHz, and with all its components logic-locked into placement locations.  Optional: By then, demonstrate 600MHz speed or higher, possibly using pseudo-dual-edge-triggered registers."
(From Dr. Frank's Cosmic Inquirer Blog)

I designed a hierarchical display in Microsoft Excel to show which of the components in the project directly utilize the PLL_clk line from the high-speed time counter and will need "logic locking".

I will start working on a separate top level file "COSMICi_FEDM_top_LogicLock_test.bdf" and begin logic locking each each of the components of the 56-bit high speed counter.a  My personal computer is not licensed for all Quartus features so I will have to use one of the computers at the CoE to test the Logic Locking implementation out, but for now I will finish reading up on how best to apply it to the FEDM  (page 88 in Quartus II Handbook and 43 pages from the Manual uploaded to the altera_docs folder).

In essence the LogicLocking feature consists of designating specific regions as "LogicLock Regions".  These regions will be registered in a table showing the status of each.

That's all she wrote.

Timing Sync Datapath

Today I worked with David Grosby (one of the interns) on finishing up the code modifications to the timing sync datapath VHDL code.

First off, we created a new version of the timing sync component, "tsedge_datapath_v2_56".  Inside this block David and I modified the "stream_pulse_data_tsedge_56" VHDL code.  The "last_thresh" input was commented out of the component, along with the " send_nlevels" and "which_thresh" variable.  Whilst modifying the code to suit the timing sync needs and requirements, the variable "send_nlevels" was deemed unnecessary and removed completely.  This shortened a lot of the code needed for the functionality of the timing component.

After we finished with our modifications we gave the code to Dr. Frank to integrate into the top14.bdf for testing with Darryl's testing code ("stream_pulse_out_test") as well.  At first there was an error with the test component where the range was defined as 0 to 3 but attempted to go to 5.  This was corrected for the natural range to go to 4 and eliminated the 5 case.  After these corrections the code was tested with the overall FEDM design and no longer gets stuck on a hold, but still isn't working properly.  Some more debugging may have to be done on these components.

That's all folks.

In the beginning...

This blog will act as the Engineering Log for my EEL4914C and EEL4915C Senior Design Class.