Timing Sync Datapath

Today I worked with David Grosby (one of the interns) on finishing up the code modifications to the timing sync datapath VHDL code.

First off, we created a new version of the timing sync component, "tsedge_datapath_v2_56".  Inside this block David and I modified the "stream_pulse_data_tsedge_56" VHDL code.  The "last_thresh" input was commented out of the component, along with the " send_nlevels" and "which_thresh" variable.  Whilst modifying the code to suit the timing sync needs and requirements, the variable "send_nlevels" was deemed unnecessary and removed completely.  This shortened a lot of the code needed for the functionality of the timing component.

After we finished with our modifications we gave the code to Dr. Frank to integrate into the top14.bdf for testing with Darryl's testing code ("stream_pulse_out_test") as well.  At first there was an error with the test component where the range was defined as 0 to 3 but attempted to go to 5.  This was corrected for the natural range to go to 4 and eliminated the 5 case.  After these corrections the code was tested with the overall FEDM design and no longer gets stuck on a hold, but still isn't working properly.  Some more debugging may have to be done on these components.

That's all folks.