Working on Logic Lock

After some testing and debugging Dr. Frank solved the issue that was occurring with Darryl, David and I's changes to the Timing Sync Datapath and test VHDL code.  Since that is working we are moving on to the next few steps.  The nearest projected self imposed deadline is:

"On or before Wednesday Feb 8th: Demonstrate the 56-bit high-speed counter running at 500MHz, and with all its components logic-locked into placement locations.  Optional: By then, demonstrate 600MHz speed or higher, possibly using pseudo-dual-edge-triggered registers."
(From Dr. Frank's Cosmic Inquirer Blog)

I designed a hierarchical display in Microsoft Excel to show which of the components in the project directly utilize the PLL_clk line from the high-speed time counter and will need "logic locking".

I will start working on a separate top level file "COSMICi_FEDM_top_LogicLock_test.bdf" and begin logic locking each each of the components of the 56-bit high speed counter.a  My personal computer is not licensed for all Quartus features so I will have to use one of the computers at the CoE to test the Logic Locking implementation out, but for now I will finish reading up on how best to apply it to the FEDM  (page 88 in Quartus II Handbook and 43 pages from the Manual uploaded to the altera_docs folder).

In essence the LogicLocking feature consists of designating specific regions as "LogicLock Regions".  These regions will be registered in a table showing the status of each.

That's all she wrote.