Dr. Frank said there was some confusion between Juan and I and he redid some of the same changes of the project I made so nothing has changed from Thursday. Quartus is installed on the new hard drive from Juan so we can utilize that computer for faster compiles later on. I will pick up from there and continue making changes from Thursday.
Things that have been accomplished so far:
►Moved cs_combine up from pulse_prep_56.bdf to add into the pulseform_cap_56_hs.bdf file since it was all alone in the previous block diagram
►Isolated all the se_pulse_cap_56 files into a separate file and rewired each one to the high_speed_counter clock line
►Created a block file called high_speed_components.bf to keep all the se_pulse_cap_56 components together in a high speed file
►Created a block file called pulseform_cap_56_hs.bdf to keep all the cs_combine components on one level
Things to be completed:
►Create hs_cons1-5 lines in pulseform_cap_56_hs as outputs
►Remove different clock inputs to the se_pulse_cap_56 components so that they have the same fed input from the clock (this was my misunderstanding that we created different inputs)
►Configure icdp 1, 2 and 3, rewiring pins
►Configure tsdp, rewring pins
Currently adding hs_cons[1..5] output bus and labeling appropriate lines in the pulseform_cap hs bdf file. This involved renaming each hs_cons line with a 1 through 5 and then creating the bus output line. Simple enough.
Removing the pins for the se_pulse hs_counter lines and making them all the same inputs. Added a pulse_in line to the TSDP as well since this was missing. high_speed_components.bdf file looks about complete so I will create a clock for this and move on to the individual datapaths now. Each se_pulse has its needed 7 input pins placed out on the bdf.
•The outputs that will be fed to the cs_combines are as follows:
→rise_s
→rise_c
→fall_s
→fall_c
→h_prod
Started redoing pmt_icdp_datapath_2_56 and renamed it to "pmt_idcp_datapath2_56_LS.bdf to signify that this is a collection of just the LOW SPEED components. All of the HIGH SPEED components have been isolated to the high_speed_components block. Each input data path is going to need pins for each of the outputs from the se_pulses. Since the cscnt_carry and cscnt_sum lines were needed for the se_pulse component they will be removed from each datapath LS component block.
•Removing the following pins for each icdp:
→cscnt_sum
→cscnt_carry
→thresh_pulse
→pll_clk
•Incorporating the following pins for each icdp:
→hs_cons (Each needs its own set of hs_cons_dp1,2,3 etc to be redirected on the top level (can rename them appropriately on the top level))
Added pulseform_cap_56_HS and redirected the hs_cons lines to the se_pulse components
Changed hs_cons[5..1] to an input rather than an output pin.inside pulseform_cap.
Back to the high_speed_components page to rename all the hs_cons lines to their appropriate inputs and channels
pmt_ic_datapath_v3_56_LS.bdf has been finished as far as I can see until compiling the file. I am going to make some changes now to the pin arrangement to the pmt_v2 file and the ts_edge input path as well.
Starting on pmc_ic_datapath2_56_LS.bdf file. Removing the same pins that weren't needed in v3. Finished removing a few pins adding in a few pins, similar to v3 and created the icdp datapaths and incorporated them onto the top level diagram top16_HSEntity.
Moving on to the Timing Sync datapath. Creating a new pulse_prep_56 design for the TSDP on the datapth block.
Removed the thresh_pulse and neg_inputs by mistake going back and reincorporating those. This will have to be done a bit differently since it is at the se_pulse level and will be added to the lines. I will come back to this later...............
Back to editing the TSDP:
The cs_combine component was moved up similar to the other components.
Time to go though, so I will pick up later on this....
Still to be done:
Need to reconfigure tsdp
Fix the negative_inputs to apply to the se_pulse lines
Tweak around with the pins a bit more and discover other things that need to be done >.<
Tuesday, March 27, 2012
Thursday, March 22, 2012
Further Renaming of HS Entity
Juan and David did some more renaming on Wednesday so today I will pick up where they left off.
Starting with the hs_components block I and going to add output pins to all of the components. 20 for each ICDP and 4 for the TSDP so 64 pins in total.... renamed all the output pins from c1i1 to c1o2 since they are outputs and not input. Applied this to all output pins on this block. Realized we may not need these inputs since the icdp and tsdp all take the same cscnt_sum and carry signal. Created different pulse values for each input
Added differing pulse lines to each of the se_pulse_preps c1i1_pulse_in etc for each of the data paths and timing path. Renamed the signals coming into the se_pulse's "PLL_clk" to match the high speed clk signal coming out from the high speed time counter.
Spent a lot of time checking line paths and updating a few more lines in the other HS block component levels. Will have to pick up some more next week. Have to spend some time on my E-fields lab pre-lab before that class starts.
Starting with the hs_components block I and going to add output pins to all of the components. 20 for each ICDP and 4 for the TSDP so 64 pins in total.... renamed all the output pins from c1i1 to c1o2 since they are outputs and not input. Applied this to all output pins on this block. Realized we may not need these inputs since the icdp and tsdp all take the same cscnt_sum and carry signal. Created different pulse values for each input
Added differing pulse lines to each of the se_pulse_preps c1i1_pulse_in etc for each of the data paths and timing path. Renamed the signals coming into the se_pulse's "PLL_clk" to match the high speed clk signal coming out from the high speed time counter.
Spent a lot of time checking line paths and updating a few more lines in the other HS block component levels. Will have to pick up some more next week. Have to spend some time on my E-fields lab pre-lab before that class starts.
Tuesday, March 20, 2012
Redesigning the High Speed Components as One Entity
So the previous design didn't quite get the operational frequency up to 500+MHz. The next approach is to build all the high speed components together in one separate entity and have all the slow speed components outside of this one entity block. This will force Quartus to keep the routing of information between the high-speed components solely between these components and not slow them down with the slow speed components.
The current working directory is on David's account on the virtual machine. On the desktop is a older called "Current Quartus Design". Then in the file "Files 3-12-2012" is where the currently worked on code is at.
Creating a bdf called "high_speed_components.bdf" where I will place all the high-speed parts to be created into one final block to play on the top level. This is where all the work I will do today will stem from.
Checked under MegaWizard Functions to see if the my_pll.v file was still set to 500MHz under the 3 tab
Output clocks. It is still at 500 MHz.
Created Separate blocks for all the "se_pulse_cap.bdf"'s to represent each of the ICDP's and a different one for the TSDP.
Redesigned a new pulse prep "pulse_prep_56_hs.bdf" to include several pins needed to take input from the high speed components se_pulse_prep.bdf's. Since the pulse_prep files now only have a bunch of in/out pins and one block diagrm this has become a redundant block and will be moved up a level into "pulse_cap_56_hs.bdf".
Removed all "cscnt_pipeline_register_56.bdf"'s since they did not make a big enough difference to the time anyways. From pulse_form_cap file i removed the following pins:
csc_sum[55..0]
csc_carry[56..1]
pll_clock
wave[1..6]
After removing pulse_prep all together I am replacing them with the cs_combine blocks. Deleted pulse_prep_56_hs.bdf since we no longer needed it and I created it thinking we would.
One final task for the "high_speed_components.bdf" labeling will be o name each se_pulse_preps lines as 1-6 for the ICDP's. These can even be placed into a block of their own for each ICDP and TSDP to reduce the overwhelming amount of se_pulse_preps on the high_speed_components page.
For "pmt_ic_datapath2" I removed cscnt_sum and cscnt_carry because this was just being passed all the way down to se_pulse_prep. Instead this signal will be rewired on the high_speed_components level with the se_pulse_preps.
Still needs finishing:
Completing the rest of the pin lines for each se_pulse_prep
Create new design blocks and place them in to the design
Still needs finishing:
Completing the rest of the pin lines for each se_pulse_prep
Create new design blocks and place them in to the design
Tuesday, March 13, 2012
Working On New Design Partition
Dr. Frank explained the idea behind the Design partition Editor. The first part is setting up the partitions for all the high-speed components:
Top: COSMICi_FEDM_top15 Source File Not Applicable
hspeed_counter_56 hspeed_counter_56 Source File Not Applicable
pmt_ic_datapath2_56 pmt_ic_datapath2_56 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst21 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst23 Source File Not Applicable
tsedge_datapath_v2_56 tsedge_datapath_v2_56 Source File Not Applicable
In each of these partitions only the dependent components of the high_speed_clock (se_pulse_caps, 6 in each icdp and 1 in the tsedge) are included. These will need to be compiled separately from the slow speed parts which will be ignored with this method for now until it all can be fit on the board. This method allows us to "ignore" the slow speed components without actually going through the project and deleting all the components that aren't needed at this phase.
After all the components have been fit onto the board and compiled. The netlist type for TOP ONLY should be set to empty. This compile will be to ensure that all components fit. i.e.:
Top: COSMICi_FEDM_top15 Empty Not Applicable
Compile again and this time with Top set to empty it will exclude the slow speed logic that was not designated in the design partition below. This should finish with a time corner slow of over 500MHz to be at where we need it.
Then the partitions included in the top design should be changed to locked placement and routing post strict fit to preserve these settings. i.e.:
hspeed_counter_56 hspeed_counter_56 Post-Fit (Strict) Placement and Routing
A final compile will have to be done with these components to ensure the settings withhold. edit: Dr. Frank also would like these partitions placed into the logic locked root region once they are all running at 500MHz. Without using Logic Lock if the slow speed components are added in they reduce the overall speed. Merging the individual components might be a problem so don't do this before logic locking. The compilation at this point should have Top set back to source file with the other components at their new settings to maintain their optimized settings with all components involved.
Once the partitions are compiled with the new settings change Top back from empty to Source File and compile once more. This will reincorporate the low_speed logic.
Working on the files that Juan and Aarmondas were working on yesterday. They got most of the partitions placed and then Aarmondas did some compiling and said there was a fitter error. The Designed called for about 78 more LAB's than were available so I am recompiling it with the 6th pulse_prep block removed from the project. Added a gnd line and 2 constant blocks to the broken lines.
After removing the 6th pulse_prep block I also added in the cscnt_pipeline_register_56 block to the 3 ICDP's and TSEdge components. Then I removed all the se_pulse_cap_56 instatiations from their respected datapath parents on the partition editor and put them all under the top level as their parent instead. Just deleting the parent partitions moved the se_pulse_cap_5's up a level into the Top partition.
My_pll was set to 200MHz as the output and not 500MHz so I have to recompile it again with those settings changed..... There were also some problem pins that had to be removed: AA19, AB19, AA21 and 2 others.
Recompiling with Top level set to empty and all other sub levels set to Source File. The next step will be to logic lock these regions with their new settings and change top back to source before recompiling.
Another error came from "Top" being empty so to fix this under Assignments-->Settings-->Compilation Process Settings-->Incremental Compilation
Uncheck the choice for "Automatically export design partition after compilation".
Compile worked successfully with a Slow Max of 683.88MHz. Adding in the 4 cscnt_pipeline_registers to the design partition screen and recompiling one more time. Next will be to add the logic locking to these and their new settings before switching top back to source.
After compiling with the se_pulse_cap and cscnt_pipeline_register the clock time was at 578.32MHz. Dragging each component onto the Root Region tab on the logic Lock menu put a lock on each of the high-speed logic components. All settings were changed to Post-Fit(strict) and Placement and Routing for these components. Top was set back to Source File and the file compilation is underway (hopefully).
Some documentation on the Design partitioner is:
http://www.altera.com/literature/manual/archives/intro_to_quartus2.pdf
Another Day, Another Compilation... ♪♫♪♫♪♫♪♫
Top: COSMICi_FEDM_top15 Source File Not Applicable
hspeed_counter_56 hspeed_counter_56 Source File Not Applicable
pmt_ic_datapath2_56 pmt_ic_datapath2_56 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst21 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst23 Source File Not Applicable
tsedge_datapath_v2_56 tsedge_datapath_v2_56 Source File Not Applicable
In each of these partitions only the dependent components of the high_speed_clock (se_pulse_caps, 6 in each icdp and 1 in the tsedge) are included. These will need to be compiled separately from the slow speed parts which will be ignored with this method for now until it all can be fit on the board. This method allows us to "ignore" the slow speed components without actually going through the project and deleting all the components that aren't needed at this phase.
After all the components have been fit onto the board and compiled. The netlist type for TOP ONLY should be set to empty. This compile will be to ensure that all components fit. i.e.:
Top: COSMICi_FEDM_top15 Empty Not Applicable
Compile again and this time with Top set to empty it will exclude the slow speed logic that was not designated in the design partition below. This should finish with a time corner slow of over 500MHz to be at where we need it.
Then the partitions included in the top design should be changed to locked placement and routing post strict fit to preserve these settings. i.e.:
hspeed_counter_56 hspeed_counter_56 Post-Fit (Strict) Placement and Routing
A final compile will have to be done with these components to ensure the settings withhold. edit: Dr. Frank also would like these partitions placed into the logic locked root region once they are all running at 500MHz. Without using Logic Lock if the slow speed components are added in they reduce the overall speed. Merging the individual components might be a problem so don't do this before logic locking. The compilation at this point should have Top set back to source file with the other components at their new settings to maintain their optimized settings with all components involved.
Once the partitions are compiled with the new settings change Top back from empty to Source File and compile once more. This will reincorporate the low_speed logic.
Working on the files that Juan and Aarmondas were working on yesterday. They got most of the partitions placed and then Aarmondas did some compiling and said there was a fitter error. The Designed called for about 78 more LAB's than were available so I am recompiling it with the 6th pulse_prep block removed from the project. Added a gnd line and 2 constant blocks to the broken lines.
After removing the 6th pulse_prep block I also added in the cscnt_pipeline_register_56 block to the 3 ICDP's and TSEdge components. Then I removed all the se_pulse_cap_56 instatiations from their respected datapath parents on the partition editor and put them all under the top level as their parent instead. Just deleting the parent partitions moved the se_pulse_cap_5's up a level into the Top partition.
My_pll was set to 200MHz as the output and not 500MHz so I have to recompile it again with those settings changed..... There were also some problem pins that had to be removed: AA19, AB19, AA21 and 2 others.
Recompiling with Top level set to empty and all other sub levels set to Source File. The next step will be to logic lock these regions with their new settings and change top back to source before recompiling.
Another error came from "Top" being empty so to fix this under Assignments-->Settings-->Compilation Process Settings-->Incremental Compilation
Uncheck the choice for "Automatically export design partition after compilation".
Compile worked successfully with a Slow Max of 683.88MHz. Adding in the 4 cscnt_pipeline_registers to the design partition screen and recompiling one more time. Next will be to add the logic locking to these and their new settings before switching top back to source.
After compiling with the se_pulse_cap and cscnt_pipeline_register the clock time was at 578.32MHz. Dragging each component onto the Root Region tab on the logic Lock menu put a lock on each of the high-speed logic components. All settings were changed to Post-Fit(strict) and Placement and Routing for these components. Top was set back to Source File and the file compilation is underway (hopefully).
Some documentation on the Design partitioner is:
http://www.altera.com/literature/manual/archives/intro_to_quartus2.pdf
Another Day, Another Compilation... ♪♫♪♫♪♫♪♫
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