Dr. Frank said there was some confusion between Juan and I and he redid some of the same changes of the project I made so nothing has changed from Thursday. Quartus is installed on the new hard drive from Juan so we can utilize that computer for faster compiles later on. I will pick up from there and continue making changes from Thursday.
Things that have been accomplished so far:
►Moved cs_combine up from pulse_prep_56.bdf to add into the pulseform_cap_56_hs.bdf file since it was all alone in the previous block diagram
►Isolated all the se_pulse_cap_56 files into a separate file and rewired each one to the high_speed_counter clock line
►Created a block file called high_speed_components.bf to keep all the se_pulse_cap_56 components together in a high speed file
►Created a block file called pulseform_cap_56_hs.bdf to keep all the cs_combine components on one level
Things to be completed:
►Create hs_cons1-5 lines in pulseform_cap_56_hs as outputs
►Remove different clock inputs to the se_pulse_cap_56 components so that they have the same fed input from the clock (this was my misunderstanding that we created different inputs)
►Configure icdp 1, 2 and 3, rewiring pins
►Configure tsdp, rewring pins
Currently adding hs_cons[1..5] output bus and labeling appropriate lines in the pulseform_cap hs bdf file. This involved renaming each hs_cons line with a 1 through 5 and then creating the bus output line. Simple enough.
Removing the pins for the se_pulse hs_counter lines and making them all the same inputs. Added a pulse_in line to the TSDP as well since this was missing. high_speed_components.bdf file looks about complete so I will create a clock for this and move on to the individual datapaths now. Each se_pulse has its needed 7 input pins placed out on the bdf.
•The outputs that will be fed to the cs_combines are as follows:
→rise_s
→rise_c
→fall_s
→fall_c
→h_prod
Started redoing pmt_icdp_datapath_2_56 and renamed it to "pmt_idcp_datapath2_56_LS.bdf to signify that this is a collection of just the LOW SPEED components. All of the HIGH SPEED components have been isolated to the high_speed_components block. Each input data path is going to need pins for each of the outputs from the se_pulses. Since the cscnt_carry and cscnt_sum lines were needed for the se_pulse component they will be removed from each datapath LS component block.
•Removing the following pins for each icdp:
→cscnt_sum
→cscnt_carry
→thresh_pulse
→pll_clk
•Incorporating the following pins for each icdp:
→hs_cons (Each needs its own set of hs_cons_dp1,2,3 etc to be redirected on the top level (can rename them appropriately on the top level))
Added pulseform_cap_56_HS and redirected the hs_cons lines to the se_pulse components
Changed hs_cons[5..1] to an input rather than an output pin.inside pulseform_cap.
Back to the high_speed_components page to rename all the hs_cons lines to their appropriate inputs and channels
pmt_ic_datapath_v3_56_LS.bdf has been finished as far as I can see until compiling the file. I am going to make some changes now to the pin arrangement to the pmt_v2 file and the ts_edge input path as well.
Starting on pmc_ic_datapath2_56_LS.bdf file. Removing the same pins that weren't needed in v3. Finished removing a few pins adding in a few pins, similar to v3 and created the icdp datapaths and incorporated them onto the top level diagram top16_HSEntity.
Moving on to the Timing Sync datapath. Creating a new pulse_prep_56 design for the TSDP on the datapth block.
Removed the thresh_pulse and neg_inputs by mistake going back and reincorporating those. This will have to be done a bit differently since it is at the se_pulse level and will be added to the lines. I will come back to this later...............
Back to editing the TSDP:
The cs_combine component was moved up similar to the other components.
Time to go though, so I will pick up later on this....
Still to be done:
Need to reconfigure tsdp
Fix the negative_inputs to apply to the se_pulse lines
Tweak around with the pins a bit more and discover other things that need to be done >.<
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