Redesigning the High Speed Components as One Entity

So the previous design didn't quite get the operational frequency up to 500+MHz.  The next approach is to build all the high speed components together in one separate entity and have all the slow speed components outside of this one entity block.  This will force Quartus to keep the routing of information between the high-speed components solely between these components and not slow them down with the slow speed components.

The current working directory is on David's account on the virtual machine.  On the desktop is a older called "Current Quartus Design".  Then in the file "Files 3-12-2012" is where the currently worked on code is at.

Creating a bdf called "high_speed_components.bdf" where I will place all the high-speed parts to be created into one final block to play on the top level.  This is where all the work I will do today will stem from.

Checked under MegaWizard Functions to see if the my_pll.v file was still set to 500MHz under the 3 tab

Output clocks.  It is still at 500 MHz.

Created Separate blocks for all the "se_pulse_cap.bdf"'s to represent each of the ICDP's and a different one for the TSDP.

Redesigned a new pulse prep "pulse_prep_56_hs.bdf" to include several pins needed to take input from the high speed components se_pulse_prep.bdf's.  Since the pulse_prep files now only have a bunch of in/out pins and one block diagrm this has become a redundant block and will be moved up a level into "pulse_cap_56_hs.bdf".

Removed all "cscnt_pipeline_register_56.bdf"'s since they did not make a big enough difference to the time anyways. From pulse_form_cap file i removed the following pins:

              csc_sum[55..0]

              csc_carry[56..1]

              pll_clock

              wave[1..6] 

After removing pulse_prep all together I am replacing them with the cs_combine blocks.  Deleted pulse_prep_56_hs.bdf since we no longer needed it and I created it thinking we would.

One final task for the "high_speed_components.bdf" labeling will be o name each se_pulse_preps lines as 1-6 for the ICDP's.  These can even be placed into a block of their own for each ICDP and TSDP to reduce the overwhelming amount of se_pulse_preps on the high_speed_components page.

 For "pmt_ic_datapath2" I removed cscnt_sum and cscnt_carry because this was just being passed all the way down to se_pulse_prep.  Instead this signal will be rewired on the high_speed_components level with the se_pulse_preps.

Still needs finishing:
Completing the rest of the pin lines for each se_pulse_prep
Create new design blocks and place them in to the design