Dr. Frank explained the idea behind the Design partition Editor. The first part is setting up the partitions for all the high-speed components:
Top: COSMICi_FEDM_top15 Source File Not Applicable
hspeed_counter_56 hspeed_counter_56 Source File Not Applicable
pmt_ic_datapath2_56 pmt_ic_datapath2_56 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst21 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst23 Source File Not Applicable
tsedge_datapath_v2_56 tsedge_datapath_v2_56 Source File Not Applicable
In each of these partitions only the dependent components of the high_speed_clock (se_pulse_caps, 6 in each icdp and 1 in the tsedge) are included. These will need to be compiled separately from the slow speed parts which will be ignored with this method for now until it all can be fit on the board. This method allows us to "ignore" the slow speed components without actually going through the project and deleting all the components that aren't needed at this phase.
After all the components have been fit onto the board and compiled. The netlist type for TOP ONLY should be set to empty. This compile will be to ensure that all components fit. i.e.:
Top: COSMICi_FEDM_top15 Empty Not Applicable
Compile again and this time with Top set to empty it will exclude the slow speed logic that was not designated in the design partition below. This should finish with a time corner slow of over 500MHz to be at where we need it.
Then the partitions included in the top design should be changed to locked placement and routing post strict fit to preserve these settings. i.e.:
hspeed_counter_56 hspeed_counter_56 Post-Fit (Strict) Placement and Routing
A final compile will have to be done with these components to ensure the settings withhold. edit: Dr. Frank also would like these partitions placed into the logic locked root region once they are all running at 500MHz. Without using Logic Lock if the slow speed components are added in they reduce the overall speed. Merging the individual components might be a problem so don't do this before logic locking. The compilation at this point should have Top set back to source file with the other components at their new settings to maintain their optimized settings with all components involved.
Once the partitions are compiled with the new settings change Top back from empty to Source File and compile once more. This will reincorporate the low_speed logic.
Working on the files that Juan and Aarmondas were working on yesterday. They got most of the partitions placed and then Aarmondas did some compiling and said there was a fitter error. The Designed called for about 78 more LAB's than were available so I am recompiling it with the 6th pulse_prep block removed from the project. Added a gnd line and 2 constant blocks to the broken lines.
After removing the 6th pulse_prep block I also added in the cscnt_pipeline_register_56 block to the 3 ICDP's and TSEdge components. Then I removed all the se_pulse_cap_56 instatiations from their respected datapath parents on the partition editor and put them all under the top level as their parent instead. Just deleting the parent partitions moved the se_pulse_cap_5's up a level into the Top partition.
My_pll was set to 200MHz as the output and not 500MHz so I have to recompile it again with those settings changed..... There were also some problem pins that had to be removed: AA19, AB19, AA21 and 2 others.
Recompiling with Top level set to empty and all other sub levels set to Source File. The next step will be to logic lock these regions with their new settings and change top back to source before recompiling.
Another error came from "Top" being empty so to fix this under Assignments-->Settings-->Compilation Process Settings-->Incremental Compilation
Uncheck the choice for "Automatically export design partition after compilation".
Compile worked successfully with a Slow Max of 683.88MHz. Adding in the 4 cscnt_pipeline_registers to the design partition screen and recompiling one more time. Next will be to add the logic locking to these and their new settings before switching top back to source.
After compiling with the se_pulse_cap and cscnt_pipeline_register the clock time was at 578.32MHz. Dragging each component onto the Root Region tab on the logic Lock menu put a lock on each of the high-speed logic components. All settings were changed to Post-Fit(strict) and Placement and Routing for these components. Top was set back to Source File and the file compilation is underway (hopefully).
Some documentation on the Design partitioner is:
http://www.altera.com/literature/manual/archives/intro_to_quartus2.pdf
Another Day, Another Compilation... ♪♫♪♫♪♫♪♫
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