Finishing Up High Speed Design

I'm picking up from where Juan left off on Monday:

  4/02/12

- Top level (top16_HSEntity)

- Wrote all of the signal names for the big high_speed_components symbol

- Finished "connecting" channel 0 using matching signal names since using wires seemed more error prone.

- Finished "connecting" channel 1 using matching signal names since using wires seemed more error prone.

- Finished "connecting" timing sync data path using matching signal names.

- Started "connecting" channel 2: Mike Dean will probably have to finish this one

- Left to be done (from what I understand):

- "Connecting" channel 2

- Getting rid of old symbols (old datapaths and old high-speed component)

- Try an initial compile (it will probably have errors since they were so many names for the signals)

- Debug the above errors

Starting off on the top level:

~Adding the clock lines to each of the components.  Starting the inputs and outputs of the left over components...

Quartus froze on me so I am currently restarting the Virtual Box since it won't respond.  Apparently something got corrupted in the file when the program froze so I am looking through the top level diagram to see if I can salvage anything from it.  I was able to recover some of the pins that Juan had created and moved this whole design onto Dropbox so that our Highspeed and Lowspeed separation files are backed up.  I am taking Juan's project on the Asus computer and adding our components to it so we can work here instead of the slow VB on the Mac.

I have to go to a ME side presentation so I will pick up later....