Juan spent Monday in lab fixing up most of the pins that were lost from the corrupted data and re-implemented some of the missing files in the switch from the MAC to the ACER computer. He made some final touches to what he felt was left pin wise and I will try to compile the design today and hopefully put it into the partioner and then logic lock it.
Dr. Frank won't be here today so I am logging in under Juan's account to activate the license server so I can compile the design. It was under "c:/flexlm/startserver" .
The new location for our files on dropbox is dropbox/Quartus. This will backup the files to prevent future corruption issues.
I tried opening the Quartus project file from dropbox but it said I did not have read/write permissions. Tried a few things to fix it but in the end I just downloaded the file from dropbox to this account and checked to see if it would open. It did with read/write and I replaced this with the existing one in dropbox once I saw that it was working.
Now to start compiling and fix the errors....
►bit_size was not defined on channels and high-speed component block
→fixed by declaring parameter values on each channel input and high-speed components:
Properties→Parameters→ name = bit_size, setting = 15, type = unsigned int
►bit_size needs to be a number on the actual lines (not a parameter). I've tried a few alternatives, and searched for bus wire labeling techniques but it looks like I will have to rename each like 55 or 56...
→utilized the ctrl-h feature to replace bit_size-1 with 55 and bit_size with 56
►hs_prod lines were incorrectly labelled, hsprodc1[1] thru [16], in correlation to the signal coming from the component block
→renamed them correctly from hs_prod1 to 16
►hs_prod lines 1-16 coming out of the high_speed components block need to be grouped into bus lines to pass to the appropriate input channel
→ grouped hs_prod1-5 to ch0, 6-10 to ch1 and 11-15 to ch2
►hs_prod line was missing from the ts_edge block
→went into file and created new block then updated it (pin was already there, needed recreating). set hs_prod16 line to this input
►an input to the TSDP channel was off by 1 bit [56..0] as was the source from hs_component block
→renamed these to [56..1] dimensions
►inside ts_edge component rise_t value was sent to an output pin when it should be fed to the stream_pulse block
→deleted the output pin, updated the block diagram and correctly connected it
►same issue for the hs_datarec line. deleted the output pin and connected it to the in_prod_hand input to stream_pulse block, cs_bits was not needed inside LS tsedge component block,
→corrected placement of pins and added a tapped lined from the LS component to the high-speed one where it actually should be, and created int_hsprod_tapped line on highspeed components block, as well as the ts_prod line to the timing_sync component.
►cscnt_sum[bit_size-1..0] and cacnt_carry were input pins in the high_speed component block but are actually being output from the clock
→removed the pins and allowed the input to be from the high speed clock PLL_line
~~ Analysis & Synthesis 46% ~~
►next is inconsistent dimensions for hs_cons and hs_prod in icdp_datapath_v3
because there is a bus line hs_cons[1..5] and hs_prod[1..5] line I think this is giving an error with the two lines just declared as hs_cons and hs_prod
→so I added an "_icdp" to the end of the last two mentioned signals to see if this would avoid any system confusion. Added he _icdp tag to the hs_cons line going into the pulse_combine block in the pulseform_cap clock then updated the block.
►inside the icdp_datapath_v2 there was a naming inconsistency between hs_cons[1..5] and the reciever hs_cons[5..1]
→so I changed them to both be [1..5] as it was labeled on the next block. I also went to the tops level and redid all the other hs lines to match the correct labeling dimensions i.e. 10..6 instead of 6..10
►getting an error that C1_pulse and C2_pulse drives an input pin and noticed they still had dimension from [1..6]
→ so I changed C1 C2 and C3 dimensions to [1..5] since we only have 5 pulses and deleted one of the 'n' values on each of the neg input lines to correlate with the 5 pulse thresholds. I think the error was just that c1_pulse and C1_pulse are not unique names since there's no difference between the names even with capital letters so I renamed the input pins to C1_pulse_in on each (which makes sense sine C3_pulse had a 4 on the end and wasn't getting any errors.
►c3o5_rise_c[bit_size..1] output from ts_edge component didn't match the dimensions declared on the bus line c3o5_rise_c[bit_size..0]
→I renamed them to c3o5_rise_c[bit_size..1] on the bus lines
►Since I made changes to the neg_input lines the xor megafunction dimensions were off
→I changed the dimensions to 5 inputs to match this change but left it named XOR_6W
►pulseform_cap was named with HS previously but I realize that is an incorrect naming
→changed the HS to an LS tag and updated the 3 icdp blocks with this new name.
►For some reason David and I's block diagram from our changes to the VHDL file of pulse_combine_56 was not in the project (either we just didn't create one or it wasn't moved in the transfer)
→Regardless, I created a new one and removed the pins to the threshold6 levels in and out and nonexistent rise and fall values, as well as hs_rec6. This was changed in both versions of the pmt_icdp blocks and I tied the other files requiring threshold6 to grounds for now to save on time.
►got an error that C1_pulse did not exist
→forgot to update the block and re-implement so I did
►Error: Width mismatch in port "C1_pulse_in[1..5]" of instance "inst11" and type high_speed_components -- source is ""pf0[0],pf0[2],pf0[3],pf0[4],pf0[5],OFF""
→ removed the OFF signal since I removed the 6th level initially.
next error up is:
►Error: Partition hierarchy "tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst1" does not exist in the current design or refers to an inferred hierarchy
→ these were deleted from the design so I will need to find them and fully remove them.....
I have to get back to the e-school as well as change into my dress clothes to help with the ME presentation, and get ready for my E-Fields lab at 6 so I will have to continue this next week on Tuesday.
Almost done debugging.....
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