Continued Debugging

I'll be picking up where I left off last week with debugging Juan and I's last attempt at speeding the operating clock to 500MHz or more.

From last week this was the current bug I was working on:


►Error: Partition hierarchy "tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst1" does not exist in the current design or refers to an inferred hierarchy
→ these were deleted from the design so I will need to find them and fully remove them..... They were in the partition editor window and needed to be deleted.

►Error with the hs_prod 1-16 value pins
→Created these into bus values to correspond with the values coming out from the high_speed_component block

►TS_SE source line was missing
→Added an output pin to the high_speed block for the sync_error line from the TS_edge component

►csbits[1..0] was named incorrectly to match with the other pins
→re-named with cs_bits[1..0] instead

►Somehow the pulseform_cap pins got disconnected from their pins
→just had to move over the pine lines to their respective pins to fix this error

►PMT_icdp_datapath_2 also had this error with disconnections of the pins from the lines
→Reconnected the pins to their respective lines to fix this error as well

►PMT_icdp_datapath_v3 also had this error with disconnections of the pins from the lines
→Reconnected the pins to their respective lines to fix this error as well


►hs_rec had no source pin
→added a pin to the tsedge block to allow input from the se_pulse block to the cs_combine block.  took the output line from high_speed_components called "" and labelled it "int_prod_hs" and fed it in to the ts_edge block.

►all the input pins in the high_speed block were labelled incorrectly 'hs_cons_icdp11'. they need to be correctly labelled to reflect their respective bus lines.
→"hs_cons_icdp1[1]" "hs_cons_icdp1[2]" etc... should fix this problem

just as a preemptive fix I grouped all the hs_prod1 through 16 lines into their own bus values so there is only one output pin instead of 16


►Error: Net "TS_ENABLE", which fans out to "high_speed_components:inst11", cannot be assigned more than one value
→TS_ENABLE was being directed to tsedge_datapath and had input from the NIOS and a vcc line

►This line needed to be only driven by the TS_ENABLE line for now rather than the vcc

~~~~~~~~~~~~~~ Analysis and Synthesis 100% ~~~~~~~~~~~~~~~~~

Project compiled fully. Now to use the partition editor and logic locking on the high_speed_component block.

Compiling the design with the top level at Source File and the high_speed_component is at Source File as well.

Next compile, top level has been changed to "Empty" and the high_speed_components was dragged to the root_region of the Logic Locking workspace.  High_speed_components was kept at Source File.

Slow_corner was 258MHz and needs to be over 500 at this point.  Re-initiating the cscnt_pipeline_registers for each input.

Pipeline registers have been incorporated into the high_speed design.  1 for each input channel.

That's all I could do today.  Will try more Thursday but will have to leave early for my E-Fields lab Final.

EDIT:  E-fields exam is at 2pm till 4pm so I will not be able to come to lab on Thursday.