Finally Achieved 500+MHz

Worked with Juan today in lab and we got the FEDM to operate at 537.35MHz  We finished getting the desired zones into the logic locked regions and created an archived file of the project with this 500+ MHz on the group blog.  We have our Hardware displaying today with Dr. Arora so we are now preparing for that and will continue on the project after spring break.

More Circuit VHDL Shifting

Worked on some more relocating of circuit elements with Darryl.  We continued working on the circuit design that Juan and David had designed with Dr. Frank on Monday.  There were a number of compiler errors that were not finished yesterday so Darryl and myself spend some cleaning these up and added in the usual missing files.

Managed to fit most of the blocks onto the logic locking squares but did not get the entire desired areas to fit.

Trying Logic Lock Techniques

Darryl and I have the same Quartus Setup now with Q9.1 as well as the SP2 (Service Pack 2) upgrade.  I am going to test each of the datapaths with the high speed counter to see if they have a higher speed when logic locked with the clock.  So far, with all the components logic locked onto the test file the classic timing analyzer returned a whopping 246MHz which is only half way to where we need it to be.  Darryl will be testing the components by themselves to see how they perform solo.

Darryl and I did some testing adding the individual channels to the top level with the high-speed counter (HSC).    By adding in just the CH0 ICDP the clocked timing frequency was 238MHz.  When adding the timing-sync DP to the top level and logic locking that as well the frequency rose to 240MHz, but is still not enough.  Adding the CH1 ICDP to the top level did not change the frequency when logic locked.  In fact the root region space that was allocated was used up and the logic lock region was not able to allocated space to CH1 with the Auto fit setting on.

This scraps the whole idea of logic locking the entire top level project since there won;t be enough space.  We will have to try and reduce the code for the components that utilize the PLL_clock line and allow for less gates to be created.  Also we will have to go inside each of the components that utilize the PLL_Line and individually lock those components to save on space.

We tested several cases with the HSC and the lower level pulse_prep and se_pulse_cap modules being logic locked and got to a frequency of 328MHz.  Will have to finish up later as I have to get to my E-Fields lab.

Implementing Logic Lock

Juan, David and Aarmondas did some initial logic locking on the high-speed counter yesterday. Today Darryl and i are going to continue working on this.  I am taking what Juan did yesterday and applying it to the Logic_Lock top level of the COSMICi gelware.

Dr. Frank recommended just putting all of the components into one logic locked region without the CPU and just testing that to see if that alone would raise the frequency to 500MHz or higher.

The testing yesterday was done in a separate file with just the high-speed counter and none of the other channels.  We can just add the other channels to the project and test those separately.

Things we need to download for syncronization between the programmers:
Altera Quartus 9.1 and 9.1 sp2
         ftp://ftp.altera.com/outgoing/release
         91_quartus_windows.exe             2.7GB 10/28/09  12:00:00 AM
         91sp2_quartus_windows.exe        2.1GB 3/26/10   12:00:00 AM
Python 3.1 version (latest release)
        http://www.python.org/download/releases/3.1.4/
 stay with the 3.1 version don't go to 3.2      

The Stratix Chip settings were set to AUTO on the dropbox files and the LogicLock test Archive file.  This had to be corrected to the appropriate chip device otherwise the actual timing results could be for any Stratix chip and be irrelevant to the one we are using.  

The number for the chip should be:

                         Stratix II: EP2S30F484C3N

Until we download the correct version of Quartus it's not worth making any test files to avoid any inconsistencies in the programs.  Darryl and I made some updates to the LogicLock Test 1 file by adding on the 4 input channels and compiled them.  I am uploading an archive file of it for Juan to continue with Wednesday.

I went through the start up process for testing the boards with Dr. Frank and wrote a step by step guide which I will also post up a bit later.

Individual Work

Decided not to meet today with Darryl since we wouldn't be ready until 3pm and this would leave us about 30-45 minutes of actual work time before I had to leave for Senior Design class.  So we will just work at our respective locations individually and share any insights found with one another today.

So far I have gotten Quartus to allow me to add the desired components to the LogicLock regions window.  The only issue so far is that you can't properly cascade some of the blocks since they have been instantiated in multiple .bdf files and the LL window doesn't allow for copies.  I may have to rename some of the blocks if this is an issue, or LL may be smart enough to work on every instance of that block in the multiple levels it appears in.

Logic Lock Testing

Can't compile the actual code but I am trying out a few things on a test file called "COSMICi_FEDM_top_LogicLock_test" to see if I can implement the logic lock regions on it without actually compiling it.  This will be sufficient enough to get familiar with it on the actual project.

By dragging and dropping the desired components into the Logic Lock Regions window it adds a reference to the files and location.

After adding the 4 main components,  ICDP CH0-Ch3 and the TSEdgeDP I added the inner layers to the region.  Then dragged them to their parent files to create a cascade.

There seems to be an issue with the sharing of common parts within the logic locking region window.  May have to rename each part if it doesn't automatically update every component with that name.

Logic Locking Research

After doing some reading and researching how to use Logic Lock for the last few weeks I have come up with some things that will have to be done.

Initially new floorplans will have to be created: One for each of the three Input Capture Datapaths and one for the Timing Sync Datapath.
Below I will go over some of the steps that can be used to accomplish this:

1)Using the Logic Lock Region found under
                              Assignments -> LogicLock Regions Window (or Alt + L)
you can enable some logic locking features on the project.

2) On the Floorplan editor you should now be able to create a new region, and will show if any regions are incorrectly assigned.  If this occurs there is a "Repair Branch" button that can be used to fix any assignment errors.

3) After a full compilation the Heirarchy Viewer Window can be used to view the project and add to or modify existing Logic Lock regions of the project.

4) Each region has properties to be modified:


Properties       Values                                                       Behavior
State            Floating         Floating regions allow the Quartus II software to determine the region’s
                   (default),        location on the device. Locked regions represent user-defined
                    Locked         locations of a region and are illustrated with a solid boundary
                                         in the graphical floorplans. A locked region must have a fixed size.

Size             Auto              Auto-sized regions allow the Quartus II software to determine the
                  (default),         appropriate size of a region given its contents. Fixed regions have a
                  Fixed              user-defined shape and size.

Reserved   Off (default),    The reserved property allows you to define whether you can use the
                 On                   resources within a region for entities that are not assigned to the
                                         region. If the reserved property is on, only items assigned to the
                                         region can be placed within its boundaries.

Enforcement  Hard            Soft regions give more deference to timing constraints, and allow some
                     (default),      entities to leave a region if it improves the performance of the overall
                     Soft             design. Hard regions do not allow contents to be placed outside of the
                                        boundaries of the region.

Origin           Any
                    Floorplan     The origin defines the top-left corner of the LogicLock region’s placement
                    Location      on the floorplan.

These properties allow you to customize the components to act as needed for best performance.

The Altera Handbook gives some steps for the overall methodology of designing these regions also:

1. Synthesize the module using the Quartus II software or another
    synthesis tool.
2. Optimize the module in the Quartus II software.
3. Export the module and the LogicLock constraints.
4. Import all modules and LogicLock constraints into the top-level
    project.
5. Compile and verify the top-level design.

This will function as a nice quick reference when working on LogicLocking different regions.


That's a wrap.

License Server Issues

Came to lab to start applying some of the logic locking applications to the Stratix Design. Unfortunately I have been learning a bit of how to use it on a Cyclone system, but the guide says that it varies from chip to chip.  This means I'll have to tinker around with some of the different features of the Startix system compared to the Cyclone chip.

When we were about to hook up my laptop to the license server there was an issue from another license being downloaded recently.  This halted all progress and we will have to try and fix this another day before we can start locking the components on the FEDM design.

That's it for today.