Trying Logic Lock Techniques

Darryl and I have the same Quartus Setup now with Q9.1 as well as the SP2 (Service Pack 2) upgrade.  I am going to test each of the datapaths with the high speed counter to see if they have a higher speed when logic locked with the clock.  So far, with all the components logic locked onto the test file the classic timing analyzer returned a whopping 246MHz which is only half way to where we need it to be.  Darryl will be testing the components by themselves to see how they perform solo.

Darryl and I did some testing adding the individual channels to the top level with the high-speed counter (HSC).    By adding in just the CH0 ICDP the clocked timing frequency was 238MHz.  When adding the timing-sync DP to the top level and logic locking that as well the frequency rose to 240MHz, but is still not enough.  Adding the CH1 ICDP to the top level did not change the frequency when logic locked.  In fact the root region space that was allocated was used up and the logic lock region was not able to allocated space to CH1 with the Auto fit setting on.

This scraps the whole idea of logic locking the entire top level project since there won;t be enough space.  We will have to try and reduce the code for the components that utilize the PLL_clock line and allow for less gates to be created.  Also we will have to go inside each of the components that utilize the PLL_Line and individually lock those components to save on space.

We tested several cases with the HSC and the lower level pulse_prep and se_pulse_cap modules being logic locked and got to a frequency of 328MHz.  Will have to finish up later as I have to get to my E-Fields lab.