Logic Locking Research

After doing some reading and researching how to use Logic Lock for the last few weeks I have come up with some things that will have to be done.

Initially new floorplans will have to be created: One for each of the three Input Capture Datapaths and one for the Timing Sync Datapath.
Below I will go over some of the steps that can be used to accomplish this:

1)Using the Logic Lock Region found under
                              Assignments -> LogicLock Regions Window (or Alt + L)
you can enable some logic locking features on the project.

2) On the Floorplan editor you should now be able to create a new region, and will show if any regions are incorrectly assigned.  If this occurs there is a "Repair Branch" button that can be used to fix any assignment errors.

3) After a full compilation the Heirarchy Viewer Window can be used to view the project and add to or modify existing Logic Lock regions of the project.

4) Each region has properties to be modified:


Properties       Values                                                       Behavior
State            Floating         Floating regions allow the Quartus II software to determine the region’s
                   (default),        location on the device. Locked regions represent user-defined
                    Locked         locations of a region and are illustrated with a solid boundary
                                         in the graphical floorplans. A locked region must have a fixed size.

Size             Auto              Auto-sized regions allow the Quartus II software to determine the
                  (default),         appropriate size of a region given its contents. Fixed regions have a
                  Fixed              user-defined shape and size.

Reserved   Off (default),    The reserved property allows you to define whether you can use the
                 On                   resources within a region for entities that are not assigned to the
                                         region. If the reserved property is on, only items assigned to the
                                         region can be placed within its boundaries.

Enforcement  Hard            Soft regions give more deference to timing constraints, and allow some
                     (default),      entities to leave a region if it improves the performance of the overall
                     Soft             design. Hard regions do not allow contents to be placed outside of the
                                        boundaries of the region.

Origin           Any
                    Floorplan     The origin defines the top-left corner of the LogicLock region’s placement
                    Location      on the floorplan.

These properties allow you to customize the components to act as needed for best performance.

The Altera Handbook gives some steps for the overall methodology of designing these regions also:

1. Synthesize the module using the Quartus II software or another
    synthesis tool.
2. Optimize the module in the Quartus II software.
3. Export the module and the LogicLock constraints.
4. Import all modules and LogicLock constraints into the top-level
    project.
5. Compile and verify the top-level design.

This will function as a nice quick reference when working on LogicLocking different regions.


That's a wrap.