Dr. Frank recommended just putting all of the components into one logic locked region without the CPU and just testing that to see if that alone would raise the frequency to 500MHz or higher.
The testing yesterday was done in a separate file with just the high-speed counter and none of the other channels. We can just add the other channels to the project and test those separately.
Things we need to download for syncronization between the programmers:
Altera Quartus 9.1 and 9.1 sp2
ftp://ftp.altera.com/outgoing/release
91_quartus_windows.exe 2.7GB 10/28/09 12:00:00 AM
91sp2_quartus_windows.exe 2.1GB 3/26/10 12:00:00 AM
Python 3.1 version (latest release)
http://www.python.org/download/releases/3.1.4/
stay with the 3.1 version don't go to 3.2
The Stratix Chip settings were set to AUTO on the dropbox files and the LogicLock test Archive file. This had to be corrected to the appropriate chip device otherwise the actual timing results could be for any Stratix chip and be irrelevant to the one we are using.
The number for the chip should be:
Stratix II: EP2S30F484C3N
Until we download the correct version of Quartus it's not worth making any test files to avoid any inconsistencies in the programs. Darryl and I made some updates to the LogicLock Test 1 file by adding on the 4 input channels and compiled them. I am uploading an archive file of it for Juan to continue with Wednesday.
I went through the start up process for testing the boards with Dr. Frank and wrote a step by step guide which I will also post up a bit later.
I went through the start up process for testing the boards with Dr. Frank and wrote a step by step guide which I will also post up a bit later.
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