Logic Lock Testing

Can't compile the actual code but I am trying out a few things on a test file called "COSMICi_FEDM_top_LogicLock_test" to see if I can implement the logic lock regions on it without actually compiling it.  This will be sufficient enough to get familiar with it on the actual project.

By dragging and dropping the desired components into the Logic Lock Regions window it adds a reference to the files and location.

After adding the 4 main components,  ICDP CH0-Ch3 and the TSEdgeDP I added the inner layers to the region.  Then dragged them to their parent files to create a cascade.

There seems to be an issue with the sharing of common parts within the logic locking region window.  May have to rename each part if it doesn't automatically update every component with that name.