I'll be picking up where I left off last week with debugging Juan and I's last attempt at speeding the operating clock to 500MHz or more.
From last week this was the current bug I was working on:
►Error: Partition hierarchy "tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst1" does not exist in the current design or refers to an inferred hierarchy
→ these were deleted from the design so I will need to find them and fully remove them..... They were in the partition editor window and needed to be deleted.
►Error with the hs_prod 1-16 value pins
→Created these into bus values to correspond with the values coming out from the high_speed_component block
►TS_SE source line was missing
→Added an output pin to the high_speed block for the sync_error line from the TS_edge component
►csbits[1..0] was named incorrectly to match with the other pins
→re-named with cs_bits[1..0] instead
►Somehow the pulseform_cap pins got disconnected from their pins
→just had to move over the pine lines to their respective pins to fix this error
►PMT_icdp_datapath_2 also had this error with disconnections of the pins from the lines
→Reconnected the pins to their respective lines to fix this error as well
►PMT_icdp_datapath_v3 also had this error with disconnections of the pins from the lines
→Reconnected the pins to their respective lines to fix this error as well
►hs_rec had no source pin
→added a pin to the tsedge block to allow input from the se_pulse block to the cs_combine block. took the output line from high_speed_components called "" and labelled it "int_prod_hs" and fed it in to the ts_edge block.
►all the input pins in the high_speed block were labelled incorrectly 'hs_cons_icdp11'. they need to be correctly labelled to reflect their respective bus lines.
→"hs_cons_icdp1[1]" "hs_cons_icdp1[2]" etc... should fix this problem
just as a preemptive fix I grouped all the hs_prod1 through 16 lines into their own bus values so there is only one output pin instead of 16
►Error: Net "TS_ENABLE", which fans out to "high_speed_components:inst11", cannot be assigned more than one value
→TS_ENABLE was being directed to tsedge_datapath and had input from the NIOS and a vcc line
►This line needed to be only driven by the TS_ENABLE line for now rather than the vcc
~~~~~~~~~~~~~~ Analysis and Synthesis 100% ~~~~~~~~~~~~~~~~~
Project compiled fully. Now to use the partition editor and logic locking on the high_speed_component block.
Compiling the design with the top level at Source File and the high_speed_component is at Source File as well.
Next compile, top level has been changed to "Empty" and the high_speed_components was dragged to the root_region of the Logic Locking workspace. High_speed_components was kept at Source File.
Slow_corner was 258MHz and needs to be over 500 at this point. Re-initiating the cscnt_pipeline_registers for each input.
Pipeline registers have been incorporated into the high_speed design. 1 for each input channel.
That's all I could do today. Will try more Thursday but will have to leave early for my E-Fields lab Final.
EDIT: E-fields exam is at 2pm till 4pm so I will not be able to come to lab on Thursday.
Tuesday, April 17, 2012
Thursday, April 12, 2012
Compiling The Beast
Juan spent Monday in lab fixing up most of the pins that were lost from the corrupted data and re-implemented some of the missing files in the switch from the MAC to the ACER computer. He made some final touches to what he felt was left pin wise and I will try to compile the design today and hopefully put it into the partioner and then logic lock it.
Dr. Frank won't be here today so I am logging in under Juan's account to activate the license server so I can compile the design. It was under "c:/flexlm/startserver" .
The new location for our files on dropbox is dropbox/Quartus. This will backup the files to prevent future corruption issues.
I tried opening the Quartus project file from dropbox but it said I did not have read/write permissions. Tried a few things to fix it but in the end I just downloaded the file from dropbox to this account and checked to see if it would open. It did with read/write and I replaced this with the existing one in dropbox once I saw that it was working.
Now to start compiling and fix the errors....
►bit_size was not defined on channels and high-speed component block
→fixed by declaring parameter values on each channel input and high-speed components:
Properties→Parameters→ name = bit_size, setting = 15, type = unsigned int
►bit_size needs to be a number on the actual lines (not a parameter). I've tried a few alternatives, and searched for bus wire labeling techniques but it looks like I will have to rename each like 55 or 56...
→utilized the ctrl-h feature to replace bit_size-1 with 55 and bit_size with 56
►hs_prod lines were incorrectly labelled, hsprodc1[1] thru [16], in correlation to the signal coming from the component block
→renamed them correctly from hs_prod1 to 16
►hs_prod lines 1-16 coming out of the high_speed components block need to be grouped into bus lines to pass to the appropriate input channel
→ grouped hs_prod1-5 to ch0, 6-10 to ch1 and 11-15 to ch2
►hs_prod line was missing from the ts_edge block
→went into file and created new block then updated it (pin was already there, needed recreating). set hs_prod16 line to this input
►an input to the TSDP channel was off by 1 bit [56..0] as was the source from hs_component block
→renamed these to [56..1] dimensions
►inside ts_edge component rise_t value was sent to an output pin when it should be fed to the stream_pulse block
→deleted the output pin, updated the block diagram and correctly connected it
►same issue for the hs_datarec line. deleted the output pin and connected it to the in_prod_hand input to stream_pulse block, cs_bits was not needed inside LS tsedge component block,
→corrected placement of pins and added a tapped lined from the LS component to the high-speed one where it actually should be, and created int_hsprod_tapped line on highspeed components block, as well as the ts_prod line to the timing_sync component.
►cscnt_sum[bit_size-1..0] and cacnt_carry were input pins in the high_speed component block but are actually being output from the clock
→removed the pins and allowed the input to be from the high speed clock PLL_line
~~ Analysis & Synthesis 46% ~~
►next is inconsistent dimensions for hs_cons and hs_prod in icdp_datapath_v3
because there is a bus line hs_cons[1..5] and hs_prod[1..5] line I think this is giving an error with the two lines just declared as hs_cons and hs_prod
→so I added an "_icdp" to the end of the last two mentioned signals to see if this would avoid any system confusion. Added he _icdp tag to the hs_cons line going into the pulse_combine block in the pulseform_cap clock then updated the block.
►inside the icdp_datapath_v2 there was a naming inconsistency between hs_cons[1..5] and the reciever hs_cons[5..1]
→so I changed them to both be [1..5] as it was labeled on the next block. I also went to the tops level and redid all the other hs lines to match the correct labeling dimensions i.e. 10..6 instead of 6..10
►getting an error that C1_pulse and C2_pulse drives an input pin and noticed they still had dimension from [1..6]
→ so I changed C1 C2 and C3 dimensions to [1..5] since we only have 5 pulses and deleted one of the 'n' values on each of the neg input lines to correlate with the 5 pulse thresholds. I think the error was just that c1_pulse and C1_pulse are not unique names since there's no difference between the names even with capital letters so I renamed the input pins to C1_pulse_in on each (which makes sense sine C3_pulse had a 4 on the end and wasn't getting any errors.
►c3o5_rise_c[bit_size..1] output from ts_edge component didn't match the dimensions declared on the bus line c3o5_rise_c[bit_size..0]
→I renamed them to c3o5_rise_c[bit_size..1] on the bus lines
►Since I made changes to the neg_input lines the xor megafunction dimensions were off
→I changed the dimensions to 5 inputs to match this change but left it named XOR_6W
►pulseform_cap was named with HS previously but I realize that is an incorrect naming
→changed the HS to an LS tag and updated the 3 icdp blocks with this new name.
►For some reason David and I's block diagram from our changes to the VHDL file of pulse_combine_56 was not in the project (either we just didn't create one or it wasn't moved in the transfer)
→Regardless, I created a new one and removed the pins to the threshold6 levels in and out and nonexistent rise and fall values, as well as hs_rec6. This was changed in both versions of the pmt_icdp blocks and I tied the other files requiring threshold6 to grounds for now to save on time.
►got an error that C1_pulse did not exist
→forgot to update the block and re-implement so I did
►Error: Width mismatch in port "C1_pulse_in[1..5]" of instance "inst11" and type high_speed_components -- source is ""pf0[0],pf0[2],pf0[3],pf0[4],pf0[5],OFF""
→ removed the OFF signal since I removed the 6th level initially.
next error up is:
►Error: Partition hierarchy "tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst1" does not exist in the current design or refers to an inferred hierarchy
→ these were deleted from the design so I will need to find them and fully remove them.....
I have to get back to the e-school as well as change into my dress clothes to help with the ME presentation, and get ready for my E-Fields lab at 6 so I will have to continue this next week on Tuesday.
Almost done debugging.....
Dr. Frank won't be here today so I am logging in under Juan's account to activate the license server so I can compile the design. It was under "c:/flexlm/startserver" .
The new location for our files on dropbox is dropbox/Quartus. This will backup the files to prevent future corruption issues.
I tried opening the Quartus project file from dropbox but it said I did not have read/write permissions. Tried a few things to fix it but in the end I just downloaded the file from dropbox to this account and checked to see if it would open. It did with read/write and I replaced this with the existing one in dropbox once I saw that it was working.
Now to start compiling and fix the errors....
►bit_size was not defined on channels and high-speed component block
→fixed by declaring parameter values on each channel input and high-speed components:
Properties→Parameters→ name = bit_size, setting = 15, type = unsigned int
►bit_size needs to be a number on the actual lines (not a parameter). I've tried a few alternatives, and searched for bus wire labeling techniques but it looks like I will have to rename each like 55 or 56...
→utilized the ctrl-h feature to replace bit_size-1 with 55 and bit_size with 56
►hs_prod lines were incorrectly labelled, hsprodc1[1] thru [16], in correlation to the signal coming from the component block
→renamed them correctly from hs_prod1 to 16
►hs_prod lines 1-16 coming out of the high_speed components block need to be grouped into bus lines to pass to the appropriate input channel
→ grouped hs_prod1-5 to ch0, 6-10 to ch1 and 11-15 to ch2
►hs_prod line was missing from the ts_edge block
→went into file and created new block then updated it (pin was already there, needed recreating). set hs_prod16 line to this input
►an input to the TSDP channel was off by 1 bit [56..0] as was the source from hs_component block
→renamed these to [56..1] dimensions
►inside ts_edge component rise_t value was sent to an output pin when it should be fed to the stream_pulse block
→deleted the output pin, updated the block diagram and correctly connected it
►same issue for the hs_datarec line. deleted the output pin and connected it to the in_prod_hand input to stream_pulse block, cs_bits was not needed inside LS tsedge component block,
→corrected placement of pins and added a tapped lined from the LS component to the high-speed one where it actually should be, and created int_hsprod_tapped line on highspeed components block, as well as the ts_prod line to the timing_sync component.
►cscnt_sum[bit_size-1..0] and cacnt_carry were input pins in the high_speed component block but are actually being output from the clock
→removed the pins and allowed the input to be from the high speed clock PLL_line
~~ Analysis & Synthesis 46% ~~
►next is inconsistent dimensions for hs_cons and hs_prod in icdp_datapath_v3
because there is a bus line hs_cons[1..5] and hs_prod[1..5] line I think this is giving an error with the two lines just declared as hs_cons and hs_prod
→so I added an "_icdp" to the end of the last two mentioned signals to see if this would avoid any system confusion. Added he _icdp tag to the hs_cons line going into the pulse_combine block in the pulseform_cap clock then updated the block.
►inside the icdp_datapath_v2 there was a naming inconsistency between hs_cons[1..5] and the reciever hs_cons[5..1]
→so I changed them to both be [1..5] as it was labeled on the next block. I also went to the tops level and redid all the other hs lines to match the correct labeling dimensions i.e. 10..6 instead of 6..10
►getting an error that C1_pulse and C2_pulse drives an input pin and noticed they still had dimension from [1..6]
→ so I changed C1 C2 and C3 dimensions to [1..5] since we only have 5 pulses and deleted one of the 'n' values on each of the neg input lines to correlate with the 5 pulse thresholds. I think the error was just that c1_pulse and C1_pulse are not unique names since there's no difference between the names even with capital letters so I renamed the input pins to C1_pulse_in on each (which makes sense sine C3_pulse had a 4 on the end and wasn't getting any errors.
►c3o5_rise_c[bit_size..1] output from ts_edge component didn't match the dimensions declared on the bus line c3o5_rise_c[bit_size..0]
→I renamed them to c3o5_rise_c[bit_size..1] on the bus lines
►Since I made changes to the neg_input lines the xor megafunction dimensions were off
→I changed the dimensions to 5 inputs to match this change but left it named XOR_6W
►pulseform_cap was named with HS previously but I realize that is an incorrect naming
→changed the HS to an LS tag and updated the 3 icdp blocks with this new name.
►For some reason David and I's block diagram from our changes to the VHDL file of pulse_combine_56 was not in the project (either we just didn't create one or it wasn't moved in the transfer)
→Regardless, I created a new one and removed the pins to the threshold6 levels in and out and nonexistent rise and fall values, as well as hs_rec6. This was changed in both versions of the pmt_icdp blocks and I tied the other files requiring threshold6 to grounds for now to save on time.
►got an error that C1_pulse did not exist
→forgot to update the block and re-implement so I did
►Error: Width mismatch in port "C1_pulse_in[1..5]" of instance "inst11" and type high_speed_components -- source is ""pf0[0],pf0[2],pf0[3],pf0[4],pf0[5],OFF""
→ removed the OFF signal since I removed the 6th level initially.
next error up is:
►Error: Partition hierarchy "tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst1" does not exist in the current design or refers to an inferred hierarchy
→ these were deleted from the design so I will need to find them and fully remove them.....
I have to get back to the e-school as well as change into my dress clothes to help with the ME presentation, and get ready for my E-Fields lab at 6 so I will have to continue this next week on Tuesday.
Almost done debugging.....
Tuesday, April 3, 2012
Finishing Up High Speed Design
I'm picking up from where Juan left off on Monday:
4/02/12
- Top level (top16_HSEntity)
- Wrote all of the signal names for the big
high_speed_components symbol
- Finished "connecting" channel 0 using matching
signal names since using wires seemed more error prone.
- Finished "connecting" channel 1 using matching
signal names since using wires seemed more error prone.
- Finished "connecting" timing sync data path using
matching signal names.
- Started "connecting" channel 2: Mike Dean will
probably have to finish this one
- Left to be done (from what I understand):
- "Connecting" channel 2
- Getting rid of old symbols (old datapaths and old
high-speed component)
- Try an initial compile (it will probably have errors since
they were so many names for the signals)
- Debug the above errors
Starting off on the top level:
~Adding the clock lines to each of the components.
Starting the inputs and outputs of the left over components...
Quartus froze on me so I am currently restarting the Virtual
Box since it won't respond. Apparently something got corrupted in the
file when the program froze so I am looking through the top level diagram to
see if I can salvage anything from it. I was able to recover some of the
pins that Juan had created and moved this whole design onto Dropbox so that our
Highspeed and Lowspeed separation files are backed up. I am taking Juan's
project on the Asus computer and adding our components to it so we can work
here instead of the slow VB on the Mac.
I have to go to a ME side presentation so I will pick up
later....
Tuesday, March 27, 2012
Continuing High-speed Redesigning from Thursday
Dr. Frank said there was some confusion between Juan and I and he redid some of the same changes of the project I made so nothing has changed from Thursday. Quartus is installed on the new hard drive from Juan so we can utilize that computer for faster compiles later on. I will pick up from there and continue making changes from Thursday.
Things that have been accomplished so far:
►Moved cs_combine up from pulse_prep_56.bdf to add into the pulseform_cap_56_hs.bdf file since it was all alone in the previous block diagram
►Isolated all the se_pulse_cap_56 files into a separate file and rewired each one to the high_speed_counter clock line
►Created a block file called high_speed_components.bf to keep all the se_pulse_cap_56 components together in a high speed file
►Created a block file called pulseform_cap_56_hs.bdf to keep all the cs_combine components on one level
Things to be completed:
►Create hs_cons1-5 lines in pulseform_cap_56_hs as outputs
►Remove different clock inputs to the se_pulse_cap_56 components so that they have the same fed input from the clock (this was my misunderstanding that we created different inputs)
►Configure icdp 1, 2 and 3, rewiring pins
►Configure tsdp, rewring pins
Currently adding hs_cons[1..5] output bus and labeling appropriate lines in the pulseform_cap hs bdf file. This involved renaming each hs_cons line with a 1 through 5 and then creating the bus output line. Simple enough.
Removing the pins for the se_pulse hs_counter lines and making them all the same inputs. Added a pulse_in line to the TSDP as well since this was missing. high_speed_components.bdf file looks about complete so I will create a clock for this and move on to the individual datapaths now. Each se_pulse has its needed 7 input pins placed out on the bdf.
•The outputs that will be fed to the cs_combines are as follows:
→rise_s
→rise_c
→fall_s
→fall_c
→h_prod
Started redoing pmt_icdp_datapath_2_56 and renamed it to "pmt_idcp_datapath2_56_LS.bdf to signify that this is a collection of just the LOW SPEED components. All of the HIGH SPEED components have been isolated to the high_speed_components block. Each input data path is going to need pins for each of the outputs from the se_pulses. Since the cscnt_carry and cscnt_sum lines were needed for the se_pulse component they will be removed from each datapath LS component block.
•Removing the following pins for each icdp:
→cscnt_sum
→cscnt_carry
→thresh_pulse
→pll_clk
•Incorporating the following pins for each icdp:
→hs_cons (Each needs its own set of hs_cons_dp1,2,3 etc to be redirected on the top level (can rename them appropriately on the top level))
Added pulseform_cap_56_HS and redirected the hs_cons lines to the se_pulse components
Changed hs_cons[5..1] to an input rather than an output pin.inside pulseform_cap.
Back to the high_speed_components page to rename all the hs_cons lines to their appropriate inputs and channels
pmt_ic_datapath_v3_56_LS.bdf has been finished as far as I can see until compiling the file. I am going to make some changes now to the pin arrangement to the pmt_v2 file and the ts_edge input path as well.
Starting on pmc_ic_datapath2_56_LS.bdf file. Removing the same pins that weren't needed in v3. Finished removing a few pins adding in a few pins, similar to v3 and created the icdp datapaths and incorporated them onto the top level diagram top16_HSEntity.
Moving on to the Timing Sync datapath. Creating a new pulse_prep_56 design for the TSDP on the datapth block.
Removed the thresh_pulse and neg_inputs by mistake going back and reincorporating those. This will have to be done a bit differently since it is at the se_pulse level and will be added to the lines. I will come back to this later...............
Back to editing the TSDP:
The cs_combine component was moved up similar to the other components.
Time to go though, so I will pick up later on this....
Still to be done:
Need to reconfigure tsdp
Fix the negative_inputs to apply to the se_pulse lines
Tweak around with the pins a bit more and discover other things that need to be done >.<
Things that have been accomplished so far:
►Moved cs_combine up from pulse_prep_56.bdf to add into the pulseform_cap_56_hs.bdf file since it was all alone in the previous block diagram
►Isolated all the se_pulse_cap_56 files into a separate file and rewired each one to the high_speed_counter clock line
►Created a block file called high_speed_components.bf to keep all the se_pulse_cap_56 components together in a high speed file
►Created a block file called pulseform_cap_56_hs.bdf to keep all the cs_combine components on one level
Things to be completed:
►Create hs_cons1-5 lines in pulseform_cap_56_hs as outputs
►Remove different clock inputs to the se_pulse_cap_56 components so that they have the same fed input from the clock (this was my misunderstanding that we created different inputs)
►Configure icdp 1, 2 and 3, rewiring pins
►Configure tsdp, rewring pins
Currently adding hs_cons[1..5] output bus and labeling appropriate lines in the pulseform_cap hs bdf file. This involved renaming each hs_cons line with a 1 through 5 and then creating the bus output line. Simple enough.
Removing the pins for the se_pulse hs_counter lines and making them all the same inputs. Added a pulse_in line to the TSDP as well since this was missing. high_speed_components.bdf file looks about complete so I will create a clock for this and move on to the individual datapaths now. Each se_pulse has its needed 7 input pins placed out on the bdf.
•The outputs that will be fed to the cs_combines are as follows:
→rise_s
→rise_c
→fall_s
→fall_c
→h_prod
Started redoing pmt_icdp_datapath_2_56 and renamed it to "pmt_idcp_datapath2_56_LS.bdf to signify that this is a collection of just the LOW SPEED components. All of the HIGH SPEED components have been isolated to the high_speed_components block. Each input data path is going to need pins for each of the outputs from the se_pulses. Since the cscnt_carry and cscnt_sum lines were needed for the se_pulse component they will be removed from each datapath LS component block.
•Removing the following pins for each icdp:
→cscnt_sum
→cscnt_carry
→thresh_pulse
→pll_clk
•Incorporating the following pins for each icdp:
→hs_cons (Each needs its own set of hs_cons_dp1,2,3 etc to be redirected on the top level (can rename them appropriately on the top level))
Added pulseform_cap_56_HS and redirected the hs_cons lines to the se_pulse components
Changed hs_cons[5..1] to an input rather than an output pin.inside pulseform_cap.
Back to the high_speed_components page to rename all the hs_cons lines to their appropriate inputs and channels
pmt_ic_datapath_v3_56_LS.bdf has been finished as far as I can see until compiling the file. I am going to make some changes now to the pin arrangement to the pmt_v2 file and the ts_edge input path as well.
Starting on pmc_ic_datapath2_56_LS.bdf file. Removing the same pins that weren't needed in v3. Finished removing a few pins adding in a few pins, similar to v3 and created the icdp datapaths and incorporated them onto the top level diagram top16_HSEntity.
Moving on to the Timing Sync datapath. Creating a new pulse_prep_56 design for the TSDP on the datapth block.
Removed the thresh_pulse and neg_inputs by mistake going back and reincorporating those. This will have to be done a bit differently since it is at the se_pulse level and will be added to the lines. I will come back to this later...............
Back to editing the TSDP:
The cs_combine component was moved up similar to the other components.
Time to go though, so I will pick up later on this....
Still to be done:
Need to reconfigure tsdp
Fix the negative_inputs to apply to the se_pulse lines
Tweak around with the pins a bit more and discover other things that need to be done >.<
Thursday, March 22, 2012
Further Renaming of HS Entity
Juan and David did some more renaming on Wednesday so today I will pick up where they left off.
Starting with the hs_components block I and going to add output pins to all of the components. 20 for each ICDP and 4 for the TSDP so 64 pins in total.... renamed all the output pins from c1i1 to c1o2 since they are outputs and not input. Applied this to all output pins on this block. Realized we may not need these inputs since the icdp and tsdp all take the same cscnt_sum and carry signal. Created different pulse values for each input
Added differing pulse lines to each of the se_pulse_preps c1i1_pulse_in etc for each of the data paths and timing path. Renamed the signals coming into the se_pulse's "PLL_clk" to match the high speed clk signal coming out from the high speed time counter.
Spent a lot of time checking line paths and updating a few more lines in the other HS block component levels. Will have to pick up some more next week. Have to spend some time on my E-fields lab pre-lab before that class starts.
Starting with the hs_components block I and going to add output pins to all of the components. 20 for each ICDP and 4 for the TSDP so 64 pins in total.... renamed all the output pins from c1i1 to c1o2 since they are outputs and not input. Applied this to all output pins on this block. Realized we may not need these inputs since the icdp and tsdp all take the same cscnt_sum and carry signal. Created different pulse values for each input
Added differing pulse lines to each of the se_pulse_preps c1i1_pulse_in etc for each of the data paths and timing path. Renamed the signals coming into the se_pulse's "PLL_clk" to match the high speed clk signal coming out from the high speed time counter.
Spent a lot of time checking line paths and updating a few more lines in the other HS block component levels. Will have to pick up some more next week. Have to spend some time on my E-fields lab pre-lab before that class starts.
Tuesday, March 20, 2012
Redesigning the High Speed Components as One Entity
So the previous design didn't quite get the operational frequency up to 500+MHz. The next approach is to build all the high speed components together in one separate entity and have all the slow speed components outside of this one entity block. This will force Quartus to keep the routing of information between the high-speed components solely between these components and not slow them down with the slow speed components.
The current working directory is on David's account on the virtual machine. On the desktop is a older called "Current Quartus Design". Then in the file "Files 3-12-2012" is where the currently worked on code is at.
Creating a bdf called "high_speed_components.bdf" where I will place all the high-speed parts to be created into one final block to play on the top level. This is where all the work I will do today will stem from.
Checked under MegaWizard Functions to see if the my_pll.v file was still set to 500MHz under the 3 tab
Output clocks. It is still at 500 MHz.
Created Separate blocks for all the "se_pulse_cap.bdf"'s to represent each of the ICDP's and a different one for the TSDP.
Redesigned a new pulse prep "pulse_prep_56_hs.bdf" to include several pins needed to take input from the high speed components se_pulse_prep.bdf's. Since the pulse_prep files now only have a bunch of in/out pins and one block diagrm this has become a redundant block and will be moved up a level into "pulse_cap_56_hs.bdf".
Removed all "cscnt_pipeline_register_56.bdf"'s since they did not make a big enough difference to the time anyways. From pulse_form_cap file i removed the following pins:
csc_sum[55..0]
csc_carry[56..1]
pll_clock
wave[1..6]
After removing pulse_prep all together I am replacing them with the cs_combine blocks. Deleted pulse_prep_56_hs.bdf since we no longer needed it and I created it thinking we would.
One final task for the "high_speed_components.bdf" labeling will be o name each se_pulse_preps lines as 1-6 for the ICDP's. These can even be placed into a block of their own for each ICDP and TSDP to reduce the overwhelming amount of se_pulse_preps on the high_speed_components page.
For "pmt_ic_datapath2" I removed cscnt_sum and cscnt_carry because this was just being passed all the way down to se_pulse_prep. Instead this signal will be rewired on the high_speed_components level with the se_pulse_preps.
Still needs finishing:
Completing the rest of the pin lines for each se_pulse_prep
Create new design blocks and place them in to the design
Still needs finishing:
Completing the rest of the pin lines for each se_pulse_prep
Create new design blocks and place them in to the design
Tuesday, March 13, 2012
Working On New Design Partition
Dr. Frank explained the idea behind the Design partition Editor. The first part is setting up the partitions for all the high-speed components:
Top: COSMICi_FEDM_top15 Source File Not Applicable
hspeed_counter_56 hspeed_counter_56 Source File Not Applicable
pmt_ic_datapath2_56 pmt_ic_datapath2_56 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst21 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst23 Source File Not Applicable
tsedge_datapath_v2_56 tsedge_datapath_v2_56 Source File Not Applicable
In each of these partitions only the dependent components of the high_speed_clock (se_pulse_caps, 6 in each icdp and 1 in the tsedge) are included. These will need to be compiled separately from the slow speed parts which will be ignored with this method for now until it all can be fit on the board. This method allows us to "ignore" the slow speed components without actually going through the project and deleting all the components that aren't needed at this phase.
After all the components have been fit onto the board and compiled. The netlist type for TOP ONLY should be set to empty. This compile will be to ensure that all components fit. i.e.:
Top: COSMICi_FEDM_top15 Empty Not Applicable
Compile again and this time with Top set to empty it will exclude the slow speed logic that was not designated in the design partition below. This should finish with a time corner slow of over 500MHz to be at where we need it.
Then the partitions included in the top design should be changed to locked placement and routing post strict fit to preserve these settings. i.e.:
hspeed_counter_56 hspeed_counter_56 Post-Fit (Strict) Placement and Routing
A final compile will have to be done with these components to ensure the settings withhold. edit: Dr. Frank also would like these partitions placed into the logic locked root region once they are all running at 500MHz. Without using Logic Lock if the slow speed components are added in they reduce the overall speed. Merging the individual components might be a problem so don't do this before logic locking. The compilation at this point should have Top set back to source file with the other components at their new settings to maintain their optimized settings with all components involved.
Once the partitions are compiled with the new settings change Top back from empty to Source File and compile once more. This will reincorporate the low_speed logic.
Working on the files that Juan and Aarmondas were working on yesterday. They got most of the partitions placed and then Aarmondas did some compiling and said there was a fitter error. The Designed called for about 78 more LAB's than were available so I am recompiling it with the 6th pulse_prep block removed from the project. Added a gnd line and 2 constant blocks to the broken lines.
After removing the 6th pulse_prep block I also added in the cscnt_pipeline_register_56 block to the 3 ICDP's and TSEdge components. Then I removed all the se_pulse_cap_56 instatiations from their respected datapath parents on the partition editor and put them all under the top level as their parent instead. Just deleting the parent partitions moved the se_pulse_cap_5's up a level into the Top partition.
My_pll was set to 200MHz as the output and not 500MHz so I have to recompile it again with those settings changed..... There were also some problem pins that had to be removed: AA19, AB19, AA21 and 2 others.
Recompiling with Top level set to empty and all other sub levels set to Source File. The next step will be to logic lock these regions with their new settings and change top back to source before recompiling.
Another error came from "Top" being empty so to fix this under Assignments-->Settings-->Compilation Process Settings-->Incremental Compilation
Uncheck the choice for "Automatically export design partition after compilation".
Compile worked successfully with a Slow Max of 683.88MHz. Adding in the 4 cscnt_pipeline_registers to the design partition screen and recompiling one more time. Next will be to add the logic locking to these and their new settings before switching top back to source.
After compiling with the se_pulse_cap and cscnt_pipeline_register the clock time was at 578.32MHz. Dragging each component onto the Root Region tab on the logic Lock menu put a lock on each of the high-speed logic components. All settings were changed to Post-Fit(strict) and Placement and Routing for these components. Top was set back to Source File and the file compilation is underway (hopefully).
Some documentation on the Design partitioner is:
http://www.altera.com/literature/manual/archives/intro_to_quartus2.pdf
Another Day, Another Compilation... ♪♫♪♫♪♫♪♫
Top: COSMICi_FEDM_top15 Source File Not Applicable
hspeed_counter_56 hspeed_counter_56 Source File Not Applicable
pmt_ic_datapath2_56 pmt_ic_datapath2_56 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst21 Source File Not Applicable
pmt_ic_datapath_v3_56 pmt_ic_datapathv3_56_inst23 Source File Not Applicable
tsedge_datapath_v2_56 tsedge_datapath_v2_56 Source File Not Applicable
In each of these partitions only the dependent components of the high_speed_clock (se_pulse_caps, 6 in each icdp and 1 in the tsedge) are included. These will need to be compiled separately from the slow speed parts which will be ignored with this method for now until it all can be fit on the board. This method allows us to "ignore" the slow speed components without actually going through the project and deleting all the components that aren't needed at this phase.
After all the components have been fit onto the board and compiled. The netlist type for TOP ONLY should be set to empty. This compile will be to ensure that all components fit. i.e.:
Top: COSMICi_FEDM_top15 Empty Not Applicable
Compile again and this time with Top set to empty it will exclude the slow speed logic that was not designated in the design partition below. This should finish with a time corner slow of over 500MHz to be at where we need it.
Then the partitions included in the top design should be changed to locked placement and routing post strict fit to preserve these settings. i.e.:
hspeed_counter_56 hspeed_counter_56 Post-Fit (Strict) Placement and Routing
A final compile will have to be done with these components to ensure the settings withhold. edit: Dr. Frank also would like these partitions placed into the logic locked root region once they are all running at 500MHz. Without using Logic Lock if the slow speed components are added in they reduce the overall speed. Merging the individual components might be a problem so don't do this before logic locking. The compilation at this point should have Top set back to source file with the other components at their new settings to maintain their optimized settings with all components involved.
Once the partitions are compiled with the new settings change Top back from empty to Source File and compile once more. This will reincorporate the low_speed logic.
Working on the files that Juan and Aarmondas were working on yesterday. They got most of the partitions placed and then Aarmondas did some compiling and said there was a fitter error. The Designed called for about 78 more LAB's than were available so I am recompiling it with the 6th pulse_prep block removed from the project. Added a gnd line and 2 constant blocks to the broken lines.
After removing the 6th pulse_prep block I also added in the cscnt_pipeline_register_56 block to the 3 ICDP's and TSEdge components. Then I removed all the se_pulse_cap_56 instatiations from their respected datapath parents on the partition editor and put them all under the top level as their parent instead. Just deleting the parent partitions moved the se_pulse_cap_5's up a level into the Top partition.
My_pll was set to 200MHz as the output and not 500MHz so I have to recompile it again with those settings changed..... There were also some problem pins that had to be removed: AA19, AB19, AA21 and 2 others.
Recompiling with Top level set to empty and all other sub levels set to Source File. The next step will be to logic lock these regions with their new settings and change top back to source before recompiling.
Another error came from "Top" being empty so to fix this under Assignments-->Settings-->Compilation Process Settings-->Incremental Compilation
Uncheck the choice for "Automatically export design partition after compilation".
Compile worked successfully with a Slow Max of 683.88MHz. Adding in the 4 cscnt_pipeline_registers to the design partition screen and recompiling one more time. Next will be to add the logic locking to these and their new settings before switching top back to source.
After compiling with the se_pulse_cap and cscnt_pipeline_register the clock time was at 578.32MHz. Dragging each component onto the Root Region tab on the logic Lock menu put a lock on each of the high-speed logic components. All settings were changed to Post-Fit(strict) and Placement and Routing for these components. Top was set back to Source File and the file compilation is underway (hopefully).
Some documentation on the Design partitioner is:
http://www.altera.com/literature/manual/archives/intro_to_quartus2.pdf
Another Day, Another Compilation... ♪♫♪♫♪♫♪♫
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